synth_gowin - synthesis for Gowin FPGAs

    synth_gowin [options]

This command runs synthesis for Gowin FPGAs. This work is experimental.

    -top <module>
        use the specified module as top module (default='top')

    -vout <file>
        write the design to the specified Verilog netlist file. writing of an
        output file is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -nodffe
        do not use flipflops with CE in output netlist

    -nobram
        do not use BRAM cells in output netlist

    -nodram
        do not use distributed RAM cells in output netlist

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with -dff option


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/gowin/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    bram:    (skip if -nobram)
        memory_bram -rules +/gowin/bram.txt
        techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v

    dram:    (skip if -nodram)
        memory_bram -rules +/gowin/dram.txt
        techmap -map +/gowin/drams_map.v
        determine_init

    fine:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/gowin/arith_map.v
        techmap -map +/techmap.v
        abc -dff    (only if -retime)

    map_ffs:
        dffsr2dff
        dff2dffs
        opt_clean
        dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
        techmap -map +/gowin/cells_map.v
        opt_expr -mux_undef
        simplemap

    map_luts:
        abc -lut 4
        clean

    map_cells:
        techmap -map +/gowin/cells_map.v
        hilomap -hicell VCC V -locell GND G
        iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O    (unless -noiopads)
        dffinit  -ff DFF Q INIT
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    vout:
        write_verilog -nodec -attr2comment -defparam -renameprefix gen <file-name>